1. Field of the Invention
The invention relates to loop filters, and in particular to loop filters with increased capacitance.
2. Description of the Related Art
A clock generator is of great importance in modern synchronous systems, such as computer systems, and communication equipments. Phase lock loops (PLL) are widely used in frequency synthesis, clock correction, clock distribution and phase demodulation.
Generally, typical phase lock loops comprise a phase frequency detector (PFD), a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a divider. The PFD detects the transitional edge of the feedback clock and a reference clock to generate a comparison signal, such that the charge pump is charged or discharged accordingly. The loop filter then generates a control voltage according to the charge/discharge of the charge pump, and the VCO determines the frequency of the clock thereof according to the control voltage. The frequency divider performs frequency division to the clock output from the VCO and outputs the divided clock to the PFD.
The loop filter typically comprises at least one capacitor to filter noise. The greater the equivalent capacitance of the loop filter is, the lesser the bandwidth of the phase lock loop and the greater the phase margin. Meanwhile, the greater the capacitance of the loop filter is, the greater the occupied area of the capacitor.